Gate induced drain leakage (GIDL) constitutes a significant hurdle for implementation of fin field effect transistor (finFET) technology, such as when using p+ polysilicon for the gate. GIDL constitutes an off-state leakage mechanism that occurs with the gate turned off and a “1” stored in a cell associated with the transistor. GIDL is directly proportional to the gate-to-active area overlap for the access device and occurs along a shortest path between the gate and drain. GIDL may increase due to a work function difference between a p+ polysilicon gate and a n+ active area.
FIG. 32 shows a known finFET device where a fin 152 etched from an active area island 154 extends between a source region 162 and a drain region 164 of island 154. A drain junction 168 between drain region 164 and the underlying semiconductor of island 154 shows a deeper impurity region for drain 164 in comparison to the impurity region for source 162 shown by a source junction 166. Plugs 160 contacting source region 162 and drain region 164 are also shown.
A word line (not shown for simplicity) would occupy a trench 158 defining fin 152 between source region 162 and drain region 164. Plugs 160 would be electrically separated from such a word line at least by insulative spacers (which also are not shown) on sidewalls of the word line. An overlap area 170 designated by hatching on the surface of drain region 164 demonstrates the gate-to-active area overlap that would exist between a word line and drain region 164. Overlap area 170 is bounded on the bottom by drain junction 168 and on the sides and top by the physical dimensions of drain region 164.
US Patent Publication No. 2008/0099850 to Jeon describes reduction of GIDL using various complex transistor structures and processing. Jeon, as well as U.S. Pat. No. 7,026,199 to Lee and US Patent Publication No. 2008/0048262 to Lee describe fins having common dimensions in the channel region over which the word line is formed as well as the source region and drain region. Essentially, the source, channel, and drain are all in the fin. One effect of providing a fin with common dimensions for the source region, the drain region and the channel includes reducing the gate-to-active area overlap.
However, indications exist that the complex structures and processes of forming known finFET devices suffer from difficulty in implementation and little tolerance for defects. Consequently, possibilities remain for better methods of forming transistors with reduced gate-to-active area overlap and better resulting structures.